Memory devices store information in an array of memory cells. A particular location within the array can be selected by activating the appropriate column and row address. The memory array is typically divided into multiple banks of memory cells which are independently accessible. This allows for the overlapping, or pipelining, of memory accesses. Take, for example, DRAM (dynamic random access memory) devices which conventionally have multiple banks each of which can be independently pre-charged. For a read or write access to a particular bank, the bank is pre-charged independently of the other banks. The bank precharge is thus hidden behind other precharge or data transfer operations, reducing precharge latency and improving data throughput.
As the capacity of memory devices increases, so too does the number of memory banks. For example, one gigabyte DDR2 (double data rate) DRAM devices typically have either four or eight banks depending on the memory device organization. Two gigabyte DDR2 DRAM devices typically have even more banks, e.g., eight or sixteen depending on device organization. Other types of memory devices may have more or less banks. Regardless, the banks are typically fabricated on a semiconductor substrate in the most area-efficient way to maximize yields. Process variation can reduce memory device yields when the layout is not optimal. Packaging considerations must also be taken into account when selecting the layout of a multi-bank memory device. Certain package types may not be feasible depending on the memory device layout such as when the device is too long in the x-direction or too tall in the y-direction.
One conventional approach for arranging the banks of a memory device on a semiconductor substrate involves placing an equal number of memory banks above and below logic common to all banks such as bias circuitry, input/output circuitry, power regulation and distribution circuitry, control logic, decoder logic, etc. However, the memory device becomes too long in the x-direction as the number of banks increases (e.g., from eight to sixteen banks) when arranged in one upper and one lower row. Conversely, the memory device becomes too tall in the y-direction when the banks are stacked above and below the common logic in a columnar arrangement. Another conventional approach involves surrounding the common logic on all sides by memory banks in a donut-like configuration, the centermost portion of the memory device including the common logic. According to this approach, the amount of semiconductor substrate allocated to the common logic is the same as that allocated to each individual bank. Thus, the common logic occupies the same area on the semiconductor substrate as each bank. However, the common logic can often be fabricated in a far smaller space than a memory bank, rendering a portion of the substrate unused.